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Re: PLL jitter reduction and lock question for Dave I . or anyone else

Posted by Dave I on July 23, 2000 at 21:41:14

In Reply to: Re: PLL jitter reduction and lock question for Dave I . or anyone else posted by tenor39 on July 23, 2000 at 20:05:54:

The ERF pin will be high for an error condition - a parity error or biphase coding violatiom or out of lock PLL. Check it with a DMM - it should be 4-5 V when not locked and close to zero when in lock. I would normally route it through a driver to a LED but you could just connect it directly to a high efficiency LED with a series resistor to ground set for about 1 mA of current or whatever brightness you want. It would be lit when out of lock (error condition). Or wire the LED and resistor to 5V so it is lit when ERF is low to indicate lock condition.

I have used good epoxy molded tantalums and low leakage aluminum electrolytics but I think the biggest payoff is in the first few mfds. With the big caps you should use two filters, one with a small resistor and small capacitor and the other with a big resistor and big capacitor. Both networks will be in parallel. With a big enough resistor in series with the electrolytic (about 1K) you should still lock OK and the small value network helps the voltage on the PLL to build up quicker. The voltage on the FILT pin 20 is always positive so the cap should be oriented with + to pin 20.

So you still didn't answer whether you found it to sound better with the revised filter. This is a way to add some jitter rejection and I have found it effective in the early DACs I worked on. There are much more effective means to remove jitter but they are much more complex also. If you find this mod effective, you would probably also benefit from more care with the power distribution to the CS8414 as much of the incoming jitter is propogated to subsequent stages because of ground and power noise on this chip. An additional PLL in an isolated section using a good quality VCXO is the next step...:-) Keep me posted on your progress.

Dave

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