In Reply to: I don't understand this argument posted by Dave_K on July 30, 2018 at 07:08:34:
I do understand what you're getting at.All I will say is picking the Q that gives the least harmonic distortion would mean placing the idle point in the dead center of the most linear part of the dynamic curve.
That's what I would call a Class A design.
I'm not a transistor guy but the above is how Class A is described in the tube text books and WRT designing for the least inherent (before applying NFB) harmonic distortion, transistors should be no different.
This part of this thread started when I perceived that people thought that the so called "Class A" part of the operation of a Class A/B design would be the same as true Class A. It isn't and I did my best to show that. Along the way someone linked an article by Nelson Pass where he, in fact, was saying the same thing as me.
The point is, with the "Class A" part of an A/B output stage, the transistors are not biased in the dead center of the most linear part of the dynamic curve (they are instead biased and therefore operating in a less linear part of the dynamic curve) so the performance can not, will not be up to the same standard as a circuit where the transistors are biased in the dead center of the most linear part of the dynamic curve. (all other things being equal)
The concept of the above is what I was trying to get across.
Tre'
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Follow Ups
- RE: I don't understand this argument - Tre' 07/30/1807:54:59 07/30/18 (3)
- RE: I don't understand this argument - Dave_K 09:23:20 07/30/18 (2)
- Theory vs Practice - BenM 14:27:27 07/30/18 (0)
- RE: I don't understand this argument - Tre' 09:38:08 07/30/18 (0)