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He's not talking about ASRC

Howdy

He's talking about having the master clock in the DAC and having it control how fast the data is delivered to the DAC. That way there doesn't need to be a PLL derive the DAC's clock from the incoming S/PDIF (or AES/EBU, I2S, USB etc.) data/clock. I.e. there is (to a first approximation) no jitter from the incoming data. This is (more or less) the way professional DACs have worked for a long time, but it isn't possible with the more or less standard consumer single S/PDIF, AES/EBU, I2S, etc. interconnect. It is a good way to greatly lessen incoming jitter. (But unlike his optimism there is still some jitter.)

-Ted

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