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Upsamplers, DACs, jitter, shakes and analogue withdrawals, this is it.

doesn't seem quite the same

You can't do much jitter attenuation with a synchronous buffer, at least not very easily. The jitter reduction I talked about in the ASRC is there because the input and output clocks aren't synchronous, the buffer size really just controls the lower cutoff frequency. But I understand that the remaining jitter is encoded in the data, and that's why I chose the synchronous path, but with a very low cutoff point and extreme isolation between clock domains.

Thanks for the info



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