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No, the ASRC sample input buffer

ASRC does resemble a servo control loop, but my original comment was regarding ASRC topology, not PLL. I only brought in PLL to describe the synchronous clock averaging methodology in my own DAC. I was interested in your assertion that all of the input clock jitter in the ASRC is transformed to noise, since this seems to go against what the designers of the devices say in regard to the function of the input buffer used in most of the devices.

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