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In Reply to: RE: Agree, and if I might be so bold as to add... posted by jkeny on January 15, 2016 at 17:19:04:
There won't be any data drops, but there will be different numbers of idle bits between the packets, since the packet bit rate is so much higher than the 8 kHz packet rate. Presumably, in an async USB implementation there would be sufficient buffering in the USB to I2S converter module to avoid data drops.
However, I think it is a very good bet that most (maybe even all) of these modules (or the inner workings of the chips on these modules) do not handle the clocking correctly. This is just the basis of my experience over decades in dealing with many digital logic designers, only a few of which were smart enough and/or obsessive enough to understand the issues involved in their true depth. At one time it was the CPU designers who ran into these issues because they were pressing the limits, but later it was the interface designers (communications and disk subsystems) that ran into the problem because they were dealing with distributed devices and central clocking was difficult if not impossible. We were trying to make computer systems that would operate correctly days, then weeks and eventually years between data errors. As speeds increased this led to requirements for data error rates of 10^(-20) or lower in quality equipment. (You will still see the distinction today between computers made for consumer use where price controls vs. computers made for business or industry where reliability and data integrity rules. Many computer companies have product lines and brand names dedicated to price and other product product lines and brand names dedicated to quality and reliability.)
Tony Lauck
"Diversity is the law of nature; no two entities in this universe are uniform." - P.R. Sarkar
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Follow Ups
- RE: Agree, and if I might be so bold as to add... - Tony Lauck 01/15/1617:46:19 01/15/16 (1)
- RE: Agree, and if I might be so bold as to add... - jkeny 18:19:40 01/15/16 (0)
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